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| Product Flyer Mixed Signal Division MB86626 KeyWaveTMAFE ADSL Analog Front End The Fujitsu MB86626 KeyWaveTMAFE ADSL Analog Front End is a complete analog front end for ADSL modems. The device integrates high resolution analog to digital converters (ADC) and digital to analog converters (DAC), and combined with active filtering significantly reduces the requirements placed on external components. The architecture supports both analog and digital echo cancellation (EC). The MB86626 KeyWaveTMAFE is ideal for cost sensitive Remote Terminal (RT) and power sensitive Central Office (CO) equipment. January 2002 Version 1.2 FME/MS/ADSLAFE/FL_1/4282 PLASTIC PACKAGE LQFP-80 FEATURES * Integrates all active circuits except transmit line driver * Programmable for G.dmt (1 channel) or G.lite (2 channel) * Low power, 3.3V operation - from 235mW/ch (2 channel CO G.lite) to 525mW (RT G.dmt) * Integrated filters and 15-bit A/D & D/A converters * 0 to +38 dB AGC range for receive channel * Supports analog and digital echo cancellation * Excellent SFDR and input noise * 0.35m CMOS technology with Triple Well * Industrial temperature range (-40 C to +85 C) ORDERING INFORMATION Part MB86626 Datasheet Order Number Contact Sales MB86626PFV DK86626-2 Contact Sales APPLICATIONS * ADSL modems * Programmable for several DSL variants (e.g. G.dmt, G.lite and G.Shdsl) * Single solution for both CO and RT * FDM and echo cancelling systems * Co-exists with ISDN * Analog modem function using second channel (RT G.lite) MB86626 KeyWaveTMAFE MB86626 Development Kit DK86626-2 Development Kit User Manual Copyright (c) 2002 Fujitsu Microelectronics Europe GmbH Page 1 of 6 Disclaimer: The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering.The information and circuit diagrams in this document are presented "as is", no license is granted by implication or otherwise. January 2002 Version 1.2 FME/MS/ADSLAFE/FL_1/4282 MB86626 KeyWaveTMAFE ADSL Analog Front End Functional Description The analog circuitry consists of two 15-bit DACs with associated anti-imaging filters, two 15-bit ADCs with anti-aliasing filters and two programmable gain summing amplifiers (PGA). A clock multiplier and bandgap reference are incorporated on-chip. A configurable data interface allows for high speed data transfer of the receive/transmit data, while a serial interface is provided for control and configuration. All analog signal paths are differential. This highly integrated device reduces the number of components required for the line interface to a transmit line driver and a small number of passive components. Analog echo cancellation at the RT attenuates the transmit echo at the input of the PGA allowing higher gain before the ADC. This gives lower receiver noise on long lines. A functional block diagram is shown in Figure 1. The device is manufactured in a 0.35m CMOS process with Triple Well extension giving improved isolation between analog blocks and digital-analog. 15 DAC PA Control 15 Tx1 PAC1 Tx2 PA Control PAC2 Rx1 Data Interface Data Interface Tx/EC/Rx data DAC 16 15 ADC 15 PGA ADC PGA Trim Rx2 Rx Test P Rx Test M R/W* Sync. Clk. In VCXO Clock Generator Serial Control I/F 4 VCXO Control Voltage Reference Ext. Ref. Serial Control Figure 1 KeyWaveTMAFE Functional Block Diagram Page 2 of 6 Copyright (c) 2002 Fujitsu Microelectronics Europe GmbH Disclaimer: The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering.The information and circuit diagrams in this document are presented "as is", no license is granted by implication or otherwise. January 2002 Version 1.2 FME/MS/ADSLAFE/FL_1/4282 MB86626 KeyWaveTMAFE ADSL Analog Front End Transmit and Receive Channel The receiver front end has constant resistance programmable attenuators on both receive inputs to allow for variable line lengths, and to maintain sufficient dynamic range in the programmable gain low noise summing amplifiers. Anti-aliasing filters are included which have programmable cut-off frequency and gain control. SNR can be improved by matching the line impedance with the use of the hybrid balance trim input which reduces echo signals prior to analog/digital echo cancellation being applied. The ADC uses a proprietary error correcting successive approximation architecture (patent applied for). In the Central Office the ADC conversion rates are halved compared to Remote Terminal equipment to reduce power consumption. The attenuators, summing amplifier and filter give a total gain from input to ADC of 0 to +38dB. The transmit path features dual DACs and anti-imaging filters with programmable cut-off frequency and gain. The dual DACs can be configured for oversampling parallel operation for Central Office use, by internally summing the two Tx outputs. For Remote Terminal the DACs are used independently for transmit and echo cancellation. Data and Serial Control Interfaces Data is transferred to and from the device via a 16-bit data bus. This bus can be configured as either two byte-wide uni-directional data buses, with one byte for transmit and echo cancellation data and one byte for receive data, or a single 16-bit bi-directional bus. The device configuration registers are programmed via a 4-wire serial interface. These registers are 16-bit wide, and are individually accessed using an 8-bit address and control word. Data may be written to or read from each of these registers. Clock Multiplier The device requires a clock source which may be an external reference, or a VCXO which can be locked to the line symbol rate. The internal clock multiplier generates an internal clock which is then divided down to provide all required internal and interface clocks. The clock multiplier is a delay line based design and therefore provides no rejection of input clock jitter. VCXO Control The integral VCXO control provides an effective means of controlling an external VCXO clock source. This digital output uses a first order Sigma-Delta DAC programmed from a 20-bit register. External RC filtering would normally be provided. Comparator Function The KeyWaveTMAFE features a differential comparator which, for example, may be used to detect whether the telephone on the subscriber line is `on or off hook'. Copyright (c) 2002 Fujitsu Microelectronics Europe GmbH Page 3 of 6 Disclaimer: The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering.The information and circuit diagrams in this document are presented "as is", no license is granted by implication or otherwise. January 2002 Version 1.2 FME/MS/ADSLAFE/FL_1/4282 MB86626 KeyWaveTMAFE ADSL Analog Front End Application Configurations 15 DAC PA Control Tx Transmit Line Driver 15 DAC PA Control Tx Transmit Line Driver Tx/EC Rx data 16 15 DAC PA Control 15 ADC 15 ADC PGA PGA Data Interface Tx/EC Rx data 16 15 DAC PA Control 15 ADC 15 ADC PGA PGA Data Interface ECout Twisted Pair line PA Control To Passive Hybrid Line Interfaces Page 4 of 6 Disclaimer: The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering.The information and circuit diagrams in this document are presented "as is", no license is granted by implication or otherwise. ADSL Modem ADSL Modem ADSL Modem Twisted Pair line Passive Hybrid ECin PGA PGA PGA PGA Passive Hybrid Trim Rx Trim Rx Clock Generator Serial Control I/F Voltage Reference Trim+ Tx+ Simplified Hybrid Circuit Clock Generator Serial Control I/F Voltage Reference Trim+ Tx+ Simplified Hybrid Circuit VCXO Control 4 VCXO Control RxRx+ Line+ Line- 4 RxRx+ Line+ Line- Ref. Clock 17.664MHz Configuration and control interface TxTrim- VCXO 17.664MHz Configuration and control interface TxTrim- Central Office Remote Terminal Figure 2 Full Rate ADSL (G.dmt) 15 DAC Transmit Line Drivers Tx 1 Tx/EC Rx data 16 15 DAC PA Control 15 DAC PA Control 15 ADC 15 ADC PGA PGA Tx Transmit Line Driver Tx/EC Rx data 16 15 DAC PA Control 15 ADC 15 ADC PGA PGA Data Interface Tx 2 Analog Modem (option) Passive Hybrid Data Interface ADSL Modem Twisted Pair line PGA PGA Rx 2 PGA PGA Rx 1 Trim Rx Clock Generator Serial Control I/F Voltage Reference Clock Generator Serial Control I/F Voltage Reference Trim+ Tx+ Simplified Hybrid Circuit VCXO Control 4 VCXO Control 4 RxRx+ Line+ Line- Ref. Clock 17.664MHz Configuration and control interface VCXO 17.664MHz Configuration and control interface TxTrim- Central Office (x2) Figure 3 G.lite Remote Terminal Copyright (c) 2002 Fujitsu Microelectronics Europe GmbH January 2002 Version 1.2 FME/MS/ADSLAFE/FL_1/4282 MB86626 KeyWaveTMAFE ADSL Analog Front End Development Kit A Development Kit, reference DK86626-2 is available for the MB86626 KeyWaveTMAFE. The board enables simple and effective evaluation of the device. The board provides a complete evaluation environment for the KeyWaveTMAFE. Connections for all analog and digital I/O signals are provided for integration into a target application, and a serial interface is provided to allow the AFE to be programmed from a host PC. Transmit channel amplifiers are available, along with a position to plug on a custom hybrid board. The Development Kit includes, * Evaluation board with MB86626 device fitted * Spare MB86626 for customer development * PC Software for KeyWaveTMAFE register programming * Serial cable, power supply connector and a comprehensive User Manual Copyright (c) 2002 Fujitsu Microelectronics Europe GmbH Page 5 of 6 Disclaimer: The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering.The information and circuit diagrams in this document are presented "as is", no license is granted by implication or otherwise. January 2002 Version 1.2 FME/MS/ADSLAFE/FL_1/4282 MB86626 KeyWaveTMAFE ADSL Analog Front End Worldwide Headquarters Japan Tel: +81 44 754 3753 Fax: +81 44 754 3329 Asia Fujitsu Limited Kamikodanaka 4-1-1 Nakahara-ku Kawasaki-shi Kanagawa-ken 211-8588 Japan Tel: +65 281 0770 Fax: +65 281 0220 Fujitsu Microelectronics Asia Pte Ltd 151 Lorong Chauan New Tech Park #05-08 Singapore 556741 http://www.fujitsu.com http://www.fmap.com.sg/ USA Tel: +1 408 922 9000 Fax: +1 408 922 9179 Europe Fujitsu Microelectronics America, Inc. 3545 North First Street San Jose CA 95134-1804 USA Tel: +49 6103 6900 Fax: +49 6103 690122 Fujitsu Microelectronics Europe GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: +1 800 866 8608 Customer Response Center Fax: +1 408 922 9179 Mon-Fri: 7am-5pm (PST) http://www.fma.fujitsu.com/ http://www.fme.fujitsu.com/ 6 The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. No license is granted by implication or otherwise under any patent or patent rights of Fujitsu Microelectronics Europe GmbH. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan. FME/MS/ADSLAFE/FL_1/4282 1.2 Page 6 of 6 Copyright (c) 2002 Fujitsu Microelectronics Europe GmbH Disclaimer: The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering.The information and circuit diagrams in this document are presented "as is", no license is granted by implication or otherwise. |
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